1. Field of the Present Invention
The present invention relates to the field of manufacture of integrated circuits, and, more particularly, to field effect transistors formed on an insulating substrate, such as silicon-on-insulator (SOI) devices, and to a method of manufacturing such devices.
2. Description of the Related Art
In modern integrated circuits, the number and, hence, the density of individual circuit elements, such as field effect transistors, is steadily increasing and, as a consequence, performance of these integrated circuits is currently improving. The increase in package density and signal performance of integrated circuits requires the reduction of critical feature sizes, such as the gate length and, thus, the channel length, of field effect transistors, to minimize the chip area occupied by a single circuit element and to reduce signal propagation delay owing to a delayed channel formation. However, currently critical feature sizes are approaching 0.1 xcexcm and less and a further improvement in circuit performance by reducing the sizes of the transistor elements is partially offset by parasitic capacitances of the transistors formed in bulk silicon substrates.
In order to meet the ever-increasing demands with respect to device and circuit performance, circuit designers have proposed new device architectures. One technique to improve performance of a circuit, for example of a CMOS device, is to manufacture the circuit on a so-called silicon-on-insulator (SOI) substrate, wherein an insulating layer is formed on a bulk substrate, for example, a silicon substrate or glass substrate, wherein frequently the insulating layer comprises silicon dioxide (also referred to as buried oxide layer). Subsequently, a silicon layer is formed on the insulating layer in which an active region for a field effect transistor device is defined by shallow trench isolation. A correspondingly fabricated transistor is entirely electrically isolated from the regions surrounding the transistor area. Contrary to a conventional device formed on a bulk semiconductor substrate, the precise spatial confinement of the active region of the SOI device significantly suppresses parasitic effects known from conventional devices, such as latch-up and leakage currents drifting into the substrate. Moreover, SOI devices are characterized by lower parasitic capacitances compared to devices formed on a bulk semiconductor substrate and, hence, exhibit an improved high-frequency performance. Moreover, due to the significantly reduced volume of the active region, radiation-induced charge carrier generation is also remarkably reduced and renders SOI devices extremely suitable for applications in radiation-intensive environments.
On the other hand, the advantages of SOI devices over conventionally fabricated devices may partially be offset by the so-called floating body effect, wherein minority charge carriers, for example, holes in an N-channel MOS transistor, are accumulated below the channel region, thereby adversely affecting the transistor characteristics, such as the threshold voltage, single-transistor-latch-up, and the like.
With reference to FIGS. 1 and 2, depicting a schematic cross-sectional view of a bulk transistor and an SOT transistor, respectively, the problems involved with typical prior art bulk MOS transistors and typical prior art SOI MOS transistors will now be explained in more detail.
In FIG. 1, an N-channel transistor 100 is formed on a silicon substrate 101. The transistor 100 comprises an active region 102 defined by shallow trench isolations 105. The active region 102 comprises a source region 103 and a drain region 104. A gate electrode 106 is formed over the active region 102 and is electrically insulated therefrom by a gate insulation layer 107. Adjacent to the gate electrode 106, sidewall spacers 108 of a dielectric material are formed. Top portions of the drain and source regions 103 and 104 and of the gate electrode 106 comprise silicided areas 109 exhibiting an increased electrical conductivity.
In operation, the drain diode formed by the N-doped drain region 104 and the P-doped active region 102 is usually reverse-biased, wherein the bias voltage may become sufficiently high to initiate a weak avalanche-breakdown. In this operation mode, electron-hole pairs are created, indicated by the minus (xe2x88x92) and plus (+) signs, respectively, in FIG. 1. In the present example of the N-channel enhancement transistor 100, the electrons may drift away with the drain current affected by the voltage applied to the source region 103 and the drain region 104. The holes, on the other hand, drift into the active region 102 and into the substrate 101. Since the active region 102 and the substrate 101 are electrically connected to ground potential via corresponding contacts (not shown), the excess charges, i.e., the holes that have drifted into the active region 102 and the substrate 101, can be drained off to avoid charge carrier accumulation and, hence, maintain the long-term stability of the transistor""s threshold voltage and drain-source breakdown voltage.
In FIG. 2, schematically depicting a cross-sectional view of a typical SOI transistor, parts similar or equivalent to those shown in FIG. 1 are indicated with like reference numerals except for a xe2x80x9c2xe2x80x9d as the leading digit rather than a xe2x80x9c1,xe2x80x9d with the explanation of those parts being omitted. In FIG. 2, the transistor 200 is formed in an active layer 201A which may be comprised of silicon, wherein a buried silicon dioxide layer 210 electrically insulates the active layer 201A and the active region 202 from the bulk substrate 201, contrary to the bulk device 100 in FIG. 1.
In operation, similarly to the transistor 100, electron-hole pairs are also created in the transistor 200, wherein, due to the dielectric isolation of the active region 202 from the substrate 201 by the buried oxide layer 210, the excess holes cannot efficiently drain off and accumulate, for example, below a channel connecting the drain region 204 and the source region 203, which forms upon application of an appropriate voltage to the gate electrode 206. The accumulated excess charge leads to characteristic kinks and increases the turn-off switch time of the device, thereby offsetting some of the advantages of SOI devices.
To overcome this drawback, conventional contacts (not shown) are formed that connect the active layer 201A and the active region 202 to a reference voltage to carry off the holes. These additional contacts, however, require further chip area and a more complex device and circuit layout, thereby significantly offsetting the improvement in chip area reduction and signal processing performance attained by reducing critical dimensions.
For this reason, it has been proposed in xe2x80x9cBandgap engineering technology for suppressing the substrate-floating-effect in 0.15 xcexcm SOI-MOSFETS,xe2x80x9d Proceedings, 1995 IEEE International SOI Conference, October 1995, by Yoshimi et al., to compensate for the floating body effect without additional body contacts by means of bandgap engineering to enhance the hole flow in the source direction by forming a silicon germanium layer in the source and drain regions. Germanium ions were implanted into the source and drain regions after gate oxidation in N-channel SOI MOSFETS. A silicon germanium layer was formed within the source and drain regions, resulting in an energy difference of the bandgap of 0.1 eV in the vicinity of the pn junction. An improvement of the drain breakdown voltage of approximately IV was obtained with this arrangement. The provision of a silicon germanium layer within the highly doped source and drain regions, however, may lead to a significantly increased resistance of these regions, thereby compromising the performance of the transistor device. This problem is exacerbated as transistor dimensions are scaled down further, requiring extremely shallow junctions at the source and drain regions.
In view of the above problems, a need exists for improved SOI transistor elements and methods of fabricating the same, whereby the adverse floating body effect may be eliminated or at least reduced without substantially compromising the transistor characteristics.
Generally, the present invention is based on the inventor""s concept to provide a recombination region having an increased density of localized recombination centers within the active region of an SOI device without comprising the crystalline quality of the remaining active region of the device.
According to one illustrative embodiment of the present invention, a field effect transistor is provided wherein the field effect transistor is formed on a substrate having formed therein an insulating layer followed by a semiconductor layer. An active region formed in the semiconductor layer includes a source region and a drain region separated by a channel region on which a gate insulation layer is formed that electrically insulates a gate electrode from the channel region. A recombination region is formed in the active region, wherein a density of recombination centers in the recombination region is higher than a density of recombination centers in the semiconductor layer.
According to a further illustrative embodiment of the present invention, a method of forming a transistor element on an insulated substrate comprises providing a substrate having formed thereon an insulating layer and forming a first and a second monocrystalline semiconductor layer on the insulating layer, wherein the first and the second monocrystalline layers have a different lattice constant to create strain in the first monocrystalline semiconductor layer. Next, a transistor element is formed in and on the first and second semiconductor layers, wherein one or more heat treatments performed during formation of the transistor element reduce the strain in the first semiconductor layer and generate a first density of point defects in the first semiconductor layer that is higher than a second density of point defects in the second semiconductor layer.